IS3S686 - Parallel and Concurrent Programming 01 Sep 2019 - 31 Aug 2025 | Version 1
Associated Module Information
| Module Code: | IS3S686 | ||
|---|---|---|---|
| Module Title: | Parallel and Concurrent Programming | ||
| Faculty: | Faculty of Computing, Engineering and Science | ||
| Faculty Group: | Information and Electronics | ||
| Faculty Sub Group: | informatics | ||
| Module Leader: | Iain Shewring | ||
| Module Team: | |||
| First Intended Intake: | SEP 2019 | Final Year of Intake: | |
| Date Closed: | |||
| Credit Value: | 20 | Credit Level: | 6 |
| Language: | English | ||
| Percentage of Module Taught in Welsh: | 0 | ||
| Equivalent Module: | |||
| HECOS codes: | |||
| HECOS Code Weighting: | |||
Document Version Information
| Version | 1 |
|---|---|
| Valid From | 01 Sep 2019 |
| Valid To | 31 Aug 2025 |
Module Aims
To introduce the theoretical and practical issues of designing and implementing parallel and concurrent systems.
Content Summary
Concurrency fundamentals:
- Non-determinism, correctness and sequential consistency.
- Concurrency in modern Operating Systems - processes, threads, remoting.
- Evaluating the performance of concurrent algorithms & Amdahl's law.
- Critical sections: mutual exclusion, progress and bounded waiting requirements.
- Atomic operations and implementing critical sections.
- Problems of deadlock, livelock and data races.
- Concurrent models: SIMD, MIMD, MISD.
- Constructs for controlling access to critical sections - Semaphores, locks, monitors.
- Message passing approaches.
- Lockless approaches.
- Transactional Memory (TM) and converting lock-based code to TM & the issues of lock scope that must be taken into account.
- Asynchronous APIs
- Functional programming comparison to imperative programming
GPGPU (General Purpose Graphics Processing Unit):
- Modelling problems for the graphics card.
- Limitations of specific commonly-used standards.
- Introduction to OpenCL , CUDA and DirectCompute.
- Introduction to writing GPGPU algorithms.
Considerations for Parallelisation:
- CPU architectures, including Intel hyper-threading & Cell architecture.
- Cache architecture & shared memory models.
- Execution models (including SIMD on traditional GPGPU architectures and MIMD on Nvidia's Fermi architecture for example).
- Distributed architectures.
Language support for parallelism and concurrency.
Learning and Teaching Methods
| Activity Type | Hours |
|---|---|
| Lecture | 10 |
| Practical classes and workshops | 10 |
| Supervised time in studio/workshop | 6 |
| Work based learning | 74 |
| Directed Study | 28 |
| Formative Assessment - Independent | 72 |
| Total Hours Selected | 200 |
Learning Outcomes
| # | Learning Outcome |
|---|---|
| LO1 | Demonstrate comprehension and analysis in the effective application of parallel and concurrent programming techniques. |
Assessment Criteria
| Assessment Category | Assessment Type | Description | Duration | Word Count | Weight (%) | Best of? | Pass Mark |
|---|---|---|---|---|---|---|---|
| Written Examination | Written Examination - Closed Book (Unseen) 1 | A test of knowledge and ability by questions not known to the candidate prior to the examination. | 150 | N/A | 50 | No | 40 |
| Written Assignment (CW) | Practical Written Work 1 | A practical exercise involving parallel and/or concurrent implementation, that draws on knowledge and material presented, supplemented by personal research and/or personal experience within the company. | 0 | 2000 | 50 | No | 40 |
Assessment Matrix
| Assessment Type | Learning Outcomes | ||
|---|---|---|---|
| LO1 | |||
| Written Examination - Closed Book (Unseen) 1 | ✔ | ||
| Practical Written Work 1 | ✔ | ||