NG4S912 - Digital Systems Design Using HDL 01 Jul 2022 - 31 Aug 2025 | Version 1

Associated Module Information

Module Code: NG4S912
Module Title: Digital Systems Design Using HDL
Faculty: Faculty of Computing, Engineering and Science
Faculty Group: Information and Electronics
Faculty Sub Group: Electronics
Module Leader: Sivagunalan Sivanathan
Module Team: Eurfyl Davies
First Intended Intake: SEP 2022 Final Year of Intake: 2024
Date Closed:
Credit Value: 20 Credit Level: 7
Language: English
Percentage of Module Taught in Welsh: 0
Equivalent Module:
HECOS codes: 100163 - electrical and electronic engineering
HECOS Code Weighting: 100

Document Version Information

Version 1
Valid From 01 Jul 2022
Valid To 31 Aug 2025

Module Aims

To provide a sound understanding of VHDL to enable the student to design and critically evaluate complex digital systems.

To enable the critical analysis of digital systems and compare and contrast the available system design approaches.

Content Summary

This module generally addresses the following content:

Digital System Design Approaches: Top-Bottom, Bottom-Up, Hierarchy, Modularity.

Introduction to System on Chip (SoC) benefiting from the Design Flexibility and IP re-use. The practical design approach for SoC and Embedded systems.

Fundamental Design Metrics: Functionality, cost, Reliability, performance and time-to-market, economic evaluation

Design representation: RTL, Managing complexity, Domains and levels of abstraction, Hierarchy, the ‘General’ Design Process

Design Cycle: Design Capture, Simulation, Synthesis, Design Organisation

Introduction to FPGAs: FPGA types, Internal Organisation, Comparison to ASICs,

Basic VHDL constructs: concurrent statement, sequential statements

Digital Building Blocks in VHDL: Registers, Counters, Multiplexers, Decoders, State Machines

Advanced VHDL: Testbenches, Design Reuse, managing design complexity using Finite State Machine (FSM)

Digital System design issues: Race conditions, Metastability, Clock Skew, Retiming, Asynchronous design challenges.

Learning and Teaching Methods

Activity Type Hours
Lecture 32
Practical classes and workshops 16
Independent Study 62
Directed Study 40
Formative Assessment - Independent 30
Active/Simulation Based 20
Total Hours Selected 200

Learning Outcomes

# Learning Outcome
LO1 Defend the methods of advanced digital design and the challenges which affect the choice of design methodology
LO2 Design and implement complex digital systems using HDL design techniques.

Module Requisites

N/A

Assessment Criteria

Assessment Category Assessment Type Description Duration Word Count Weight (%) Best of? Pass Mark
Asynchronous Assessment Practical Coursework 1 (Asynch) Coursework 0 2000 40 No 50
Synchronous Onsite Assessment (Exam) Onsite Closed Book Examination 1 Written examination 120 N/A 60 No 50

Assessment Matrix

Assessment Type Learning Outcomes
LO1 LO2
Practical Coursework 1 (Asynch) ✔ ✔
Onsite Closed Book Examination 1 ✔ ✔

Reading List

C. H. Roth and L. K. John, Digital systems design using VHDL, Third , International / Lizy Kurian John. ed. Australia : Cengage Learning, [2018].

R. Beuchat, A. Guerrieri, and S. Kashani, Fundamentals of System-on-Chip Design on Arm Cortex-M Microcontrollers. ARM Education Media, 2021.

D. Greaves, Modern System-on-Chip Design on Arm. ARM Education Media, 2021.

J. F. Wakerly, Digital Design: Principles and Practices Package. Pearson Education, Limited, 2010.

N. H. E. Weste, CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley, 2011.

M. Zwolinski, Digital System Design with VHDL. Prentice Hall, 2004.

V. A. Pedroni, Circuit Design with VHDL, third edition. MIT Press, 2020.